During the last decade, we have conducted much research in the DSE of real-time systems, developing the framework depicted in the figure above.
Let us first outline the framework phases, that is subdivided into three blocks:
(1) Profiling and Modeling,
(2) Architecture Composition and
(3) Architecture Evaluation and Optimization.
During the Profiling and Modeling phase, the component developer profiles the developed SW components at cycle-accurate instruction level and generates a performance model for each individual component.
Each performance model may target various hardware usage aspects (CPU, BUS, RAM, Network, etc.) and can be specified for multiple platforms.
Our tooling supports automated profiling and model specification, as well as the repository placement for the subsequent phases.
The architecture composition phase aims both at the selection of the required components and the automated generation of a model of the composed system using defined workload scenarios.
The composition can be performed for a number of architectural alternatives, while each alternative design includes the component instantiations and connections, as well as the mapping on a selected HW platform.
Being applied onto the critical execution scenarios, the design specification is converted into a system model.
Other challenges addressed are the support for multiple component architecture styles and provisioning of resulting composition models in common formats.
The Analysis and Optimization phase enables evaluation of system performance properties by both schedulability and simulation analysis of the obtained system models.
Both techniques support various hardware platforms, multiple scheduling policies and different network protocols.
The schedulability analysis provides guaranteed worst-case boundary conditions and can be executed within a few seconds, thereby removing the architecture alternatives that do not comply with the system's requirements.
However, it does not provide detailed behavior timeline data, average-case resource usage and corresponding latencies.
The previously mentioned metrics can be extracted by simulation techniques which provide detailed system behavior, thereby enabling identification of possible bottlenecks already at the early design phases.
However, simulation requires a substantial time span (from minutes to days), to obtain stable prediction results.
Therefore, simulation can be selectively used for a detailed exploration of specific execution problems in the architecture, such as buffering and task-interleaving problems.
Finally, the system is validated with a comparison to the requirements, leading to consequent design iteration(s).
Each iteration searches for an optimal architecture by tuning the allowed factors of freedom (SW component, hardware structure, SW/HW mapping and scheduling policies).