Cycle-Accurate Design Space Exploration on Real-Time Distributed Systems

Summary: 



Component-based real-time systems are widely adopted, as they enable rapid prototyping. A sysem architect needs accurate performance analysis methods of the composed system even at the early design phase.The performance analysis should be performed wirhin deterministic execution boundaries since that an exhaustive DSE requies evaluation of million architecture alternatives. Finally, the generaion of different architecture alternatives should be performed autmatically allowing identification of global optimal architecture alternative solution-set. In this project we have developed the ProMARTES framework that performs exhaustive DSE of component-based real-time distributed systems.

Project Description: 
Component-based real-time systems are widely adopted, as they enable rapid prototyping and development of a system. The resulting real-time systems still should meet the performance requirements, such as throughput, latency, etc. For architecture composition, the architect needs reliable assessment methods to evaluate and predict the performance of the system. An incorrect performance prediction may lead to adopting an inefficient system architecture with the consequences of system re-design or re-implementation. The Design Space Exploration (DSE) of such component-based systems is a multi-level task, since DSE incorporates: (a) the system composition from existing HW and SW blocks, (b) the performance analysis of the composed system and (c) the automated generation of architecture alternatives. The DSE of component-based systems features multiple challenges. The composed system may be based on components that are not available during design time. However, the accuracy of these abstract components/models is vital for obtaining reliable performance predictions about the behavior of the future system. Another challenge comes from the limitations of analysis mechanisms, classified in two categories: analytic/formal methods and simulation techniques. The former are not able to provide a detailed execution timeline, while the latter cannot guarantee reachability of worst cases during global optimization. Finally, due to the abundance of architecture alternatives generated by either Genetic Algorithms or simulated annealing techniques, a guided optimization technique needs to be developed.
During the last decade, we have conducted much research in the DSE of real-time systems, developing the framework depicted in the figure above. Let us first outline the framework phases, that is subdivided into three blocks: (1) Profiling and Modeling, (2) Architecture Composition and (3) Architecture Evaluation and Optimization. During the Profiling and Modeling phase, the component developer profiles the developed SW components at cycle-accurate instruction level and generates a performance model for each individual component. Each performance model may target various hardware usage aspects (CPU, BUS, RAM, Network, etc.) and can be specified for multiple platforms. Our tooling supports automated profiling and model specification, as well as the repository placement for the subsequent phases. The architecture composition phase aims both at the selection of the required components and the automated generation of a model of the composed system using defined workload scenarios. The composition can be performed for a number of architectural alternatives, while each alternative design includes the component instantiations and connections, as well as the mapping on a selected HW platform. Being applied onto the critical execution scenarios, the design specification is converted into a system model. Other challenges addressed are the support for multiple component architecture styles and provisioning of resulting composition models in common formats. The Analysis and Optimization phase enables evaluation of system performance properties by both schedulability and simulation analysis of the obtained system models. Both techniques support various hardware platforms, multiple scheduling policies and different network protocols. The schedulability analysis provides guaranteed worst-case boundary conditions and can be executed within a few seconds, thereby removing the architecture alternatives that do not comply with the system's requirements. However, it does not provide detailed behavior timeline data, average-case resource usage and corresponding latencies. The previously mentioned metrics can be extracted by simulation techniques which provide detailed system behavior, thereby enabling identification of possible bottlenecks already at the early design phases. However, simulation requires a substantial time span (from minutes to days), to obtain stable prediction results. Therefore, simulation can be selectively used for a detailed exploration of specific execution problems in the architecture, such as buffering and task-interleaving problems. Finally, the system is validated with a comparison to the requirements, leading to consequent design iteration(s). Each iteration searches for an optimal architecture by tuning the allowed factors of freedom (SW component, hardware structure, SW/HW mapping and scheduling policies).

The autonomous navigating robot exploring the VCA lab and composing a floor map on the fly.

Autonomously Navigating Robot Our Design Space Exploration Approach has been applied to an autonomously navigating robot that utilizes complex navigation and map-composition algorithms. The self-navigating robot is a distributed real-time system. The communication among the multiple nodes/components is being performed through the publish-subscribe mechanism. Using the ProMo tool, we profile the required SW components for the navigation of the robot and we automatically generate the relevant cycle-accurate and MARTE-compatible performance models. The generated performance models act as reliable sources during the composition of a number of architecture alternatives. Subsequently, we map the SW components onto different HW blocks and define 9 individual scenarios. Subsequently, in order to identify the performance of the generated architecture alternatives, we perform both schedulability and simulation analysis. We first perform schedulability analysis, for removing the architecture alternatives that do not meet the real-time requirements. The candidates that satisfy the system requirements are then evaluated with simulation analysis for the identification of the average-case execution time (ACET) and possible bottlenecks. The consecutive execution of the two analysis methods results in a set of solutions that are Pareto-optimal and satisfy the requirements of the composed system. Finally, by comparing the performance analysis results, we conclude and select the optimal architecture alternative in terms of cost, throughput and robustness.
ProMARTES Design Space Exploration method incorporates: (a) profiling and modeling of SW components at cycle-accurate level, (b) automated generation of system performance model from the models of individual components, (c) evaluation of the obtained system model by schedulability analysis and simulation techniques, resulting in predicted latencies, throughput, resource usage and robustness. The proposed profiling method provides the advantage of cycle-accurate performance measurements resulting to highly accurate performance predictions (6 % error range). Moreover, the performance models are compatible with the commonly used UML-MARTE profile \cite{website:MARTE}. The method deploys both types of analysis techniques: schedulability and simulation, enabling predictions of both guaranteed WCET and detailed behaviour of tasks. Finally, we integrate the Eclipse Papyrus IDE into our tooling pipeline, so that an architect can easily design the SW/HW architectures graphically and automatically convert the design into models. Last but not least, in the near future, we plan to integrate an automated generation of architecture alternatives increasing the design space that our framework can explore.
Application Area: 
Surveillance
Video/Imaging Discipline: 
3D processing
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